1. Field of the Invention
The present invention relates to a data-processing system and method using memory-remapping technique. Such invention is designed to reduce the workload of processors, such as central processing units (CPUs) in personal computers, and to serve the data transfer requirement of various peripheral devices.
2. Description of the Related Art
Memory is an infrastructure block in data-processing or computing systems (hereafter is referred to as xe2x80x9cthe Systemxe2x80x9d). Under normal operation, the System must spend a lot of time to move data from and write data into the memory. Therefore, how to effectively access memory is a critical issue when assessing the System""s overall performance.
FIG. 1 (Prior Art) is a block diagram which illustrates the fundamental structure of the System. As shown in FIG. 1, the System includes processor 1, system controller 3, memory 5 and several peripheral devices such as peripheral device 7 and peripheral device 9. Processor 1 is the key component in the System for performing various data-processing operations, such as arithmetic and logical operations, and data transfer operations. Memory 5, usually implemented by dynamic random access memories (hereafter referred as DRAMs), is a main storage device for storing major program codes and data. Peripheral devices 7 and 9 are used to communicate with the exterior or supplement extra functions to the System. Some popular peripheral devices, such as graphic cards, modems with I/O interface and Moving Picture Experts Group""s cards (MPEG cards), are prevalent in most computing or data-processing systems. System controller 3, which is installed between processor 1, memory 5 and peripheral devices 7 and 9, is used to link processor 1 and the peripheral devices. In addition, system controller 3 provides an accessing scheme for memory 5 to help processor 3 and the peripheral devices to access memory 5. From the viewpoint of memory accessing, system controller 3 should handle all requests ready for accessing memory 5 in the predefined timing, from either processor 1 or peripheral devices 7 and 9. It is noticed that some essential components in modern computer systems are omitted from the illustrated system architecture, such as caches in the memory hierarchy, shown in FIG. 1.
FIG. 2 (Prior Art) illustrates detail structures of system controller 3 and memory 5 in the System. In the modern memory technology, physical memory devices, such as DRAMs, are usually divided into several memory banks that can be accessed independently. As shown in FIG. 2, memory 5 is consisted of memory bank 5a, memory bank 5b, memory bank 5c, and so on, which can be accessed independently under the control of dedicated access controlling signals (not shown). On the other hand, FIG. 2 also illustrates three memory access components of system controller 3, including access control circuit 31, page management circuit 33 and open-page address table (stored in memories) 35. Access control circuit 31 is responsible for receiving external access requests, which come from either processor 1 or other peripheral devices. It is also responsible for physically executing the access control protocol of memory 5. Page management circuit 33 helps the access control circuit 31 in access controlling, especially in page management. Each page of memory 5 contains a fixed number of bytes that can be accessed in the faster operation mode. The byte number of each page depends on the practical application, usually about 32 bytes or more. If a page is xe2x80x9copenxe2x80x9d, it means that all memory locations contained in this page can be accessed (esp. the writing operation) faster than those contained in xe2x80x9cNon openxe2x80x9d pages since pre-fetch operations are not required. Open-page address table 35, which is implemented by memory devices, is used to memorize the addressing information of all xe2x80x9copenxe2x80x9d pages in memory 5. Generally speaking, page management circuit 33 can properly alter all the addressing information that is stored in open-page address table 35 according to the physical access operations of access control circuit 31. On the other hand, page management circuit 33 also assists access control circuit 31 to effectively access to memory 3, with reference to the addressing information of all open pages maintained in the open-page address table 35.
In the system architecture shown in FIG. 1, processor 1 and other peripheral devices have to frequently access to the required storage locations of memory 5 to perform desired applications. FIG. 3 (Prior Art) shows the schematic system diagram of such an access example, in which peripheral device 9 provides the System with specific data and then peripheral device 7 performs an operation on these specific data. The example illustrated in FIG. 3 can be thought of as the case that a modem device (i.e., peripheral device 9) downloads an archived video file from the Internet, such as one encoded by the MPEG scheme, and the System employs a dedicated MPEG card (i.e., peripheral device 7) to decode or recover the video data. In general system architecture, each of the peripheral devices is assigned with a dedicated segment of memory used to communicating with each other. In FIG. 3, peripheral device 7 accesses memory segment B2 by using addresses ADDR#2 that are dedicated to peripheral device 7; the peripheral device 9 accesses memory segment B1 by addresses ADDR#1 that are dedicated to peripheral device 9.
In the conventional data-processing system, there are five steps required in this example, which are denoted as S1xcx9cS5, respectively. To demonstrate the whole process, these steps are sequentially described as follows. In step S1, peripheral device 9 stores data, which may be an archived file, to the memory segment B1 mapping to the addresses ADDR#1. Next, processor 1 must move the inputted data stored in memory segment B1 to memory segment B2 mapping to the addresses ADDR#2 that are dedicated to peripheral device 7. Accordingly, processor 1 reads the data stored in memory segment B1 (step S2) and writes the data to the memory segment B2 (step S3). It is obvious that the workload of processor 1 increases since processor 1 must involve in the process of moving data. Finally, peripheral device 7 can retrieve the data currently stored in memory segment B2 (step S4), perform the desired operation on these data, such as MPEG decoding, and then write the resulting data back to memory segment B2 (step S5).
The drawback of conventional memory access mechanism is twofold. First, processor 1 must involve itself in the process of moving data between two memory segments that are individually assigned to two different peripheral devices. It means that the processor 1 must waste time to execute the required data transfer operations and delay other necessary tasks. Second, moving data from memory segment B1 to memory segment B2 is a time-consuming process. Accordingly, it is obvious that the overall system performance will be degraded due to the task of moving data between two memory segments in such an application.
An object of the present invention is to provide a method and system for facilitating data exchange between two isolated memory segments and reducing the workload and the processing time of the system processor, thereby increasing the overall performance of the System.
The present invention achieves this objective by providing an enhanced system controller that supports memory-remapping technology to the System. The memory device in the System contains a first memory segment (or first set of physical storage locations) and a second memory segment (or second sets of physical storage locations). The system controller is operated under two operating modes. In the first operating mode, also called a normal mode, the system controller maps a first set of addresses that is dedicated to the first peripheral device to the first memory segment, and maps a second set of addresses that is dedicated to the second peripheral device to the second memory segment. Such mapping relationship is the same as that in the conventional case. In the second operation mode, also called a remapping mode, the system controller changes the original relationship of the addresses to the memory segments. That is, the first set of addresses dedicated to the first peripheral device is remapped to the second memory segment and the second set of the addresses dedicated to the second peripheral device is remapped to the first memory segment. Accordingly, the second peripheral device can access the first memory segment involving data previously processed by the first peripheral device without data transfer.
Switching from the normal mode to the remapping mode is triggered by a first control signal, which can be activated in response to the case that the first peripheral device finishes accessing the first memory segment in the normal mode. Similarly, switching from the remapping mode back to the normal mode is triggered by a second control signal, which can be activated in response to the case that the second peripheral device finishes accessing the first memory segment in the remapping mode.
Furthermore, the system controller consists of an accessing device, a storage device (embedded memories) and a controlling device. The accessing device is responsible for accessing a memory device in response to access requests issued by peripheral devices. The storage device is responsible for storing a first mapping table and a second mapping table indicating the relationship of memory segments to different memory address sets. The controlling device, which is coupled to the storage device and the accessing device, must perform the following two functions. The first function is to pick up the required mapping table defining the relationship of the addressing information contained in the input requests to the memory segments from the storing device in response to the current operating mode. The second function is to cooperate with the accessing device in actually accessing the memory device by referring to the picked-up mapping table. Therefore, the memory segments, more specifically, the data stored therein, can be readily accessed by different peripheral devices in the different operating modes. No physical data transfer is required.
Moreover, the present invention provides a general processing access method requested between the first peripheral device, second peripheral device and memory device to reduce possibility of physical data transfer. First, the first set of addresses dedicated to the first peripheral device is mapped to one of the memory segments within the memory device. Then the first peripheral device can write data to this memory segment using the first set of the addresses. When the first peripheral device finishes its task, the second set of the addresses dedicated to the second peripheral device is remapped to this memory segment in place of the first set. Therefore, the second device can easily read data from this memory segment using the second set of the addresses. No data transfer between two different memory segments is needed in such process.